1. Technical Field of the Invention
The present invention relates to data storage in a memory system of a computer, and more particularly, to the control of data transfers to a memory system having at least one cache and a main memory.
2. Description of the Related Art
Modern computer systems often incorporate cache memories to take advantage of available high performance microprocessors. A cache memory is a block of very fast memory, normally high-speed static random access memory (SRAM), that is located between the microprocessor and the main memory. The data or instructions that are kept in the cache memory are those data or instructions that the microprocessor is most likely to need next. If the information the microprocessor requests next is held within the cache memory, this information can be retrieved without wait states. This is called a cache hit. If the data needed by the microprocessor is not in the cache memory, the data must be retrieved from the main memory and wait states are needed. This is called a cache miss.
One type of cache memory is a "write-through cache" (also commonly referred to as a store-through cache). In such a cache, no attempt is made to speed up a microprocessor write operation. Microprocessor write commands are pushed through the write-through cache immediately so that the data is written both to the cache and the main memory, with the normal wait-state delays, at the same time. The write-through cache is a conservative design since it guarantees that main memory and the cache are constantly in agreement.
A faster cache memory is a "writeback cache", which allows the microprocessor to write changes to the cache memory, but not necessarily to the main memory at the same time. As time allows, the data in the cache is written back to the main memory. One of the problems with the writeback cache is that there are times when a main memory and the cache memory have different contents assigned to the same memory locations.
A writeback cache is divided into smaller units, referred to as cache lines, and correspond to the lines of storage used by microprocessors. Main memory is normally divided into blocks, with cache lines in the cache corresponding to the locations within such a memory block. When data is written into the main memory, this data will then be considered to be written to a cache line. Write cycles in which a cache line of the cache is updated, but in which the data is not yet stored in the main memory, creates a cache line in the cache that is considered "dirty". In other words, a dirty cache line is one which contains data that has been updated, but has not yet been written back to the cache line in the main memory.
For systems with writeback caches, and an input/output (I/O) that writes data to main memory, it is first determined whether the cache line which is being written to is dirty, by "snooping" the cache memory. A snoop is essentially an inquiry to the cache memory requesting that a potentially dirty line be written out of the cache memory and subsequently invalidated. If the snoop cycle indicates that the cache line to which the write to main memory is being directed is a dirty line, then a writeback to main memory will be performed prior to the writing of data in the main memory. A writeback flushes the snooped cache line out of the cache memory and writes it back to the main memory. There is a latency between determining that the cache line is dirty and the commencement of a writeback. This latency is the greatest when the system has an internal cache and an external cache and the cache line is dirty in both of these caches. There is a further penalty performance when synchronization between two frequency domains is necessary, such as when the processor runs at X MHZ, and the memory controller runs at Y MHZ.
Certain computer systems, such as file server systems, contain high-speed I/O devices. In these systems, the memory subsystem performance needs to be maximized to support the data transfer rates between the main memory and the I/O channel. This is particularly important within a file server system that contains I/O devices capable of performing data streaming in which data is sent in bursts. If the memory subsystem cannot maintain the transfer of data to main memory as the same rate as the data is being supplied by the I/O device, then a bus controller will interject wait states on the bus until the memory controller is ready to accept more data.
Since the length of a burst transfer of a high-performance data streaming I/O device is normally less than the length of a cache line, cached dirty data is normally written back to main memory before the data from the I/O device is allowed to write into main memory. This writeback requires the snoop cycle, a snoop-to-writeback latency, and the actual writeback before the data can be written to the main memory by the I/O device. If the data from the I/O device were allowed to be written in main memory without performing a snoop cycle, a subsequent writeback would immediately write over the data from the I/O device. The performance of a system having a writeback cache and a high-performance I/O device is slowed due to the clock cycles required for the snoop cycle, the snoop-to-writeback latency, and the writeback of the dirty cache line prior to the writing of the data from the I/O device to main memory. Even when the snoop cycle does not detect a dirty cache line, the snoop cycle itself occupies clock cycles that reduce performance.